Imperfections in semiconductor manufacturing processes result in variations in components (e.g., cells) on a chip. Some existing design tools account for such variations, referred to as on-chip variations (OCVs). For example, instead of assuming that a path has a constant delay, some existing design tools specify a timing range that characterizes the maximum or the minimum delay of a cell. As the feature size of the chip decreases, the amount of OCVs proportionally increases. Existing design tools typically make more pessimistic assumptions in order to anticipate the worst case scenario. As a result, the entire design is penalized.
Moreover, different layout context (such as different locations on the cell) may lead to different delays. Some design tools rely on a mapping table that maps different layout contexts to different delay times, and look up the appropriate delay based on the layout. However, the values used in the mapping table still tend to be based on pessimistic assumptions and tend to penalize the entire design.
Existing place-and-route (P&R) tools typically rely on static timing analysis based on the most pessimistic assumptions. Some tools employ mean values of the components but still use pessimistic assumptions when evaluating whether the layout meets the timing constraints. The resulting layout is therefore often suboptimal.